Cadence PCIe 6.0 Subsystem on TSMC N3 Achieves First-Pass Compliance to Accelerate AI and HPC Silicon

Cadence Design Systems (Nasdaq: CDNS) has announced that its complete PCI Express® (PCIe®) 6.0 PHY and controller subsystem, implemented on TSMC’s leading-edge N3 process, achieved first-pass compliance success at PCI-SIG’s inaugural PCIe 6.0 compliance workshop. Validated at the full standard throughput of 64 GT/s in an x8 configuration, the tape-out-ready IP block has been officially added to the PCI-SIG Integrators List. By securing silicon-proven compliance on TSMC N3, Cadence provides high-performance computing (HPC) and AI hyperscale chip architects with a pre-validated, low-risk interconnect pipeline engineered to de-risk high-volume manufacturing for next-generation compute engines.

“PCI Express is a crucial scale-up interconnect for AI/HPC data centers and AI factories, and Cadence’s subsystem for the PCIe 6.0 specification delivers best-in-class performance with among the lowest power in the industry,” said Marc Loinaz, vice president of research and development for high-performance PHY, Silicon Solutions Group at Cadence. “This first-pass compliance success validates our complete PHY and controller solution and gives customers confidence that our technology is fully interoperable and ready for production.”
The milestone underscores the importance of early ecosystem collaboration in bringing new standards to market. Cadence worked closely with PCI-SIG, test equipment providers, and industry partners in the months leading up to the official compliance workshop, conducting interoperability testing to identify and resolve potential issues before the formal evaluation.
“As PCIe 6.0 technology enables the next wave of AI and high-performance computing systems, rigorous compliance and interoperability testing are essential for ecosystem success,” said Brig Asay, General Manager, Network Data Center, Keysight Technologies. “Cadence’s first-pass compliance achievement reflects both the quality of its PCIe 6.0 subsystem implementation and the effectiveness of comprehensive validation using Keysight’s test and measurement solutions. We are pleased to support industry leaders in accelerating PCIe 6.0 technology deployment with confidence.”
“Cadence is a long-standing PCI-SIG member helping to further PCIe technology adoption,” said Al Yanes, president and chairperson of PCI-SIG. “Cadence’s PCIe 6.0 compliance milestone plays a role in the continued advancement of PCIe technology architecture.”

PCIe 6.0 technology addresses growing demand for high-bandwidth connectivity in AI and high-performance computing systems, where the standard is used for accelerator cards, network interfaces, and storage devices. The interface is expected to see wide adoption in data center and AI infrastructure, with broader deployment in automotive and enterprise systems following as the ecosystem matures.

“Positron AI has licensed Cadence’s SerDes IP for the PCIe 6.0 specification for our AI inference accelerator chip,” said Thomas Sohmers, CTO at Positron AI. “Cadence’s complete PCIe 6.0 subsystem built in silicon and robust interoperability testing give us confidence that our PCIe 6.0 interface will meet the high-bandwidth connectivity demands of our transformer workloads.”
Key features of Cadence’s PCIe 6.0 technology solution include:

• Complete subsystem solution with PHY and controller built in silicon
• ADC and DSP-based equalization
• Firmware-optimized SerDes operation
• Multi-protocol flexibility and support
• Optimized for low power, including support for the latest PCI-SIG engineering change notices (ECNs)
• Certification for x8 configuration on TSMC N3 process

PCI-SIG has continued to advance the PCIe standard to meet the needs of advanced HPC and AI workloads. Cadence offers a broad portfolio of PCIe technology solutions up to the PCIe 7.0 specification.
Cadence’s complete subsystem solution for PCIe 6.0 technology, including PHY and controller, is available now for SoC providers to design in.